Design Samples
Here are a few short examples from our core components library. You may download and use it for free, even for commercial purposes/projects, there aren't restrictions either.
Line Delay Buffer
The module provides a single (one) video line delay using FPGA or ASIC internal RAM-block(s). It is written in pure (technology independent) synthesizable Verilog allowing automatic instantiation on various platforms. It was successfully used in many different projects, such as: real-time HDTV video processing module for PDP/LCD display controller ASIC, endoscope video improvement processor, MPEG2 compression pre-processing system, etc.
To download full information click here
RGB to YUV (Y/Cr/Cb) color space converter
The module provides 8-bits R G B inputs, 8-bits internal multiplying factors, and 8-bits Y/Cr/Cb output buses.
